This invention relates to a method of making a bump on a substrate, and more particularly, to a method and apparatus for pretreating a substrate prior to electroplating a film over an under bump metallurgy of the substrate.
A flip chip microelectronic assembly includes a direct electrical connection of face down (that is, xe2x80x9cflippedxe2x80x9d) electronic components onto substrates, such as ceramic substrates, circuit boards, or carriers using conductive bump bond pads of the chip. Flip chip technology is quickly replacing older wire bonding technology that uses face up chips with a wire connected to each pad on the chip.
The flip chip components used in flip chip microelectronic assemblies are predominantly semiconductor devices, however, components such as passive filters, detector arrays, and MEM devices are also being used in flip chip form. Flip chips are also known as xe2x80x9cdirect chip attachxe2x80x9d because the chip is directly attached to the substrate, board, or carrier by the conductive bumps.
The use a flip chip packaging has dramatically grown as a result of the flip chip""s advantages in size, performance, flexibility, reliability, and cost over other packaging methods and from the widening availability of flip chip materials, equipment and services. In some cases, the elimination of old technology packages and bond wires may reduce the substrate or board area needed to secure the device by up to 25 percent, and may require far less height. Further, the weight of the flip chip can be less than 5 percent of the old technology package devices.
Flip chips are advantageous because of their high-speed electrical performance when compared to other assembly methods. Eliminating bond wires reduces the delay in inductance and capacitance of the connection, and substantially shortens the current path resulting in the high speed off-chip interconnection.
Flip chips also provide the greatest input/output connection flexibility. Wire bond connections are generally limited to the perimeter of the chip or die, driving the die sizes up as a number of connections have increased over the years. Flip chip connections can use the whole area of the die, accommodating many more connections on a smaller die. Further, flip chips can be stacked in 3-D geometries over other flip chips or other components.
Flip chips also provided the most rugged mechanical interconnection. Flip chips when underfilled with an adhesive such as an epoxy, can withstand the most rugged durability testing. In addition to providing the most rugged mechanical interconnection, flip chips can be the lowest cost interconnection for high-volume automated production.
The bumps of the flip chip assembly serve several functions. The bumps provided an electrical conductive path from the chip (or die) to the substrate on which the chip is mounted. A thermally conductive path is also provided by the bumps to carry heat from the chip to the substrate. The bumps also provided part of the mechanical mounting of the chip to the substrate. A spacer is provided by the bumps that prevents electrical contact between the chip and the substrate connectors. Finally, the bumps act as a short lead to relieve mechanical strain between the chip and the substrate.
Flip chips are typically made by a process including placing solder bumps on a silicon wafer. The solder bump flip chip processing typically includes four sequential steps: 1) preparing the wafer for solder bumping; 2) forming or placing the solder bumps on the wafer; 3) attaching the solder bumped die to a board, substrate or carrier; and 4) completing the assembly with an adhesive underfill. A brief description of the prior art methods of performing the first step will provide a better background for understanding the present invention.
The first step in a typical solder bumping process involves preparing the semiconductor wafer bumping sites on bond pads of the individual integrated circuits defined in the semiconductor wafer. The preparation may include cleaning, removing insulating oxides, and preparing a pad metallurgy that will protect the integrated circuits while making good mechanical and electrical contact with the solder bump. Accordingly, protective metallurgy layers may be provided over the bond pad.
Ball limiting metallurgy (BLM) or under bump metallurgy (UBM) generally consists of successive layers of metal. The xe2x80x9cadhesionxe2x80x9d layer must adhere well to both the bond pad metal and the surrounding passivation, provide a strong, low-stress mechanical and electrical connection. The xe2x80x9cdiffusion barrierxe2x80x9d layer prevents the diffusion of solder into the underlying material. The xe2x80x9csolder wettablexe2x80x9d layer provides a wettable surface for the molten solder during the solder bumping process, for good bonding of the solder to the underlying metal.
For a substrate such as a semiconductor wafer having contact pads made from copper based materials, the UBM may include a layer of titanium over the contact pad, and a layer of copper over the titanium layer. Regardless of the type of contact pad used, additional layers may be deposited over the UBM prior to depositing an electrically conductive material such as solder over the UBM and contact pad. These additional layers are often referred to as seed layers. For a copper based contact pad having a UBM including titanium and copper layers, it is known to those skilled in the art to deposit a first seed layer comprising copper over the copper layer of the UBM, and a second seed layer comprising nickel over the copper seed layer.
FIG. 1 illustrates a prior art semiconductor wafer 10 having a base substrate 12 with devices (not shown) formed therein and metal interconnects (not shown) formed over the devices and having a bond pad or contact pad 14 near the upper surface thereof. A passivation layer 16 is provided over the semiconductor wafer and includes an opening therein exposing the upper surface of the contact pad 14. A UBM 18 is provided over and the passivation layer 16 and the contact pad 14. For a copper based contact pad 14 the UBM 18 includes a first seed layer 20, preferably including titanium, overlying the contact pad 14. A second seed layer 22 is provided over the first seed layer 20. Preferably the second seed layer 22 includes nickel. A dry film photoresist layer 24 is provided over the semiconductor wafer and includes an opening 26 formed therein down to the second seed layer 22 and overlying the UBM 18 and contact pad 14. The opening 26 formed in the dry film photoresist 24 may have a depth, as indicated by item A in FIG. 1, of 110 micrometers or greater, and the opening 26 may have a width or diameter, as indicated by item B in FIG. 1, of 100 micrometers for an aspect ratio of approximately 1.
FIG. 2 illustrates a prior art method of depositing a film or seed layer over the UBM on a semiconductor wafer described in FIG. 1. The semiconductor wafer 10 is placed in a wafer jig 28 having an opening therein exposing the upper face of the semiconductor wafer 10. The jig 28 is dipped in a plating solution 30 so that the entire wafer 10 is submerged below the plating solution 30. However, due to the small width of the opening 26 and the aspect ratio, it is difficult to completely plate the entire surface of the exposed portions of the UBM 18 (second layer 22).
It is believed that the surface tension of the plating solution molecules, for example deionized water molecules, prevents the plating solution from adequately filling the opening 26 in the dry film photoresist 24. It is also believed that due to the small width or diameter of the opening 26 (and the associated aspect ratio) air has difficulty flowing out of the opening and is trapped. The trapped air in the opening prevents the plating solution from completely filling the opening 26.
As a result, the plated first seed layer 34 is deposited only over a portion of the second layer 22 of the UBM and does not extend outwardly to meet the side walls 68 of the photoresist 24 that define the opening 26 thus leaving voids 36 as shown in FIG. 4. Thus it would be desirable to provide a method of plating a seed layer over the UBM on a substrate without producing voids in the seed layer.
A method including the step of providing a substrate having a contact pad, and an under bump metallurgy overlying the contact pad, and a photoresist layer overlying the under bump metallurgy, and wherein the photoresist layer has an opening therein down to the under bump metallurgy and aligned with the contact pad. The substrate is pretreated with the first wetting solution prior to plating a first seed layer over the under bump metallurgy. Thereafter, a first seed layer is plated onto the under bump metallurgy.
In another embodiment of the invention, step of pretreating the substrate includes spraying the substrate with the first wetting solution.
In another embodiment of the invention the step of pretreating the substrate includes spraying the substrate with the first wetting solution so that the sprayed first wetting solution includes particles having a diameter less than the diameter of the opening in the photoresist layer.
In another embodiment of the invention the opening in the photoresist layer has a diameter equal to or less than 100 micrometers and the step of pretreating includes spraying the substrate with the first wetting solution so that the sprayed first wetting solution includes particles having a diameter equal to or less than 100 micrometers.
In another embodiment of the invention the sprayed first wetting solution particles have a diameter ranging from 10-100 micrometers.
Another embodiment of the invention further includes the step of plating a second seed layer over the first seed layer.
In another embodiment of the invention the step of plating a first seed layer over the under bump metallurgy includes dipping the substrate in a plating bath.
In another embodiment of the invention the step of plating a first seed layer over the under bump metallurgy includes dipping the substrate in an electroplating bath.
Another embodiment of the invention includes a step of the pretreating the substrate having a first seed layer thereafter with the second wetting solution prior to plating a second seed layer over the first seed layer, and-further comprising plating a second seed layer over the first seed layer.
In another embodiment of the invention the step of the pretreating the substrate having a first seed layer includes spraying the substrate with a second wetting solution so that the sprayed second wetting solution includes particles having a diameter less than the diameter of the opening in the photoresist.
In another embodiment of the invention the opening in the photoresist layer has a diameter equal to or less than 100 micrometers and wherein the step of pretreating the substrate having a first seed layer includes spraying the substrate with a second wetting solution so that the sprayed second wetting solution includes particles having a diameter less than 100 micrometers.
In another embodiment of the invention the sprayed second wetting solution particles have a diameter ranging from 10-100 micrometers.
Another embodiment of the invention further includes a step of depositing an electrically conductive material over the second seed layer.
In another embodiment of the invention the first seed layer includes copper.
In another embodiment of the invention the second seed layer includes nickel.
In another embodiment of the invention the first seed layer includes copper, and the second seed layer includes nickel.
In another embodiment of the invention the under bump metallurgy includes a first and a second layer.
In another embodiment of the invention the first layer of the under bump metallurgy includes titanium, and the second layer of the under bump metallurgy includes copper.
In another embodiment of the invention the first wetting solution includes deionized water.
In another embodiment of the invention the second wetting solution includes deionized water.
Another embodiment of the invention includes an apparatus having a wafer jig constructed and arranged to carry a semiconductor wafer therein and wherein the wafer jig includes an opening therein for exposing a top surface of the semiconductor wafer. A wetting solution supply tank is connected to a pump, and the pump is connected to a spray module for spraying a wetting solution through the spray module and onto a semiconductor wafer carried in the wafer jig.
In another embodiment of the invention the spray module and the wafer jig are constructed and arranged to the movable with respect to each other.
Another embodiment of the invention further includes a wafer jig holding machine constructed and arranged for oscillating reciprocally the wafer jig in at least a vertical direction with respect to the spray module.
In another embodiment of the invention the spray module includes a plurality of spray nozzles each constructed and arranged to spray wetting solution particles each having a diameter less than 100 micrometers.
In another embodiment of the invention the spray module include a plurality of spray nozzles each constructed and arranged to spray wetting solution particles each having a diameter ranging from 10-100 micrometers.
In another embodiment of the invention the spray module includes three spray nozzles arranged in a triangular shape.